1. Field of Technology of the Invention
The present invention relates to ring oscillator circuits such as variable frequency type ring oscillator circuits and delay circuits such as variable delay circuits, and provides ring oscillator circuits with low power supply voltage dependency of the oscillation frequency and delay circuits with low power supply voltage dependency of the delay time.
2. Prior Art Technology
FIG. 5 is a diagram showing an example of a conventional variable frequency type ring oscillator circuit. In FIG. 5, Vin indicates a control voltage for controlling the oscillation frequency, and Sout an oscillation output.
The ring oscillator circuit comprises K units of inverter circuits U21, U22, . . . , U2K connected in a ring shape. In this instance, K is an odd number such as 3, 5, 7, . . . .
In FIG. 5, although the internal configurations of the inverter circuits U22, . . . , U2K are omitted except for the first-stage inverter circuit U21, all have the same circuit configuration as the first-stage inverter circuit U21.
The inverter circuit U21, as shown in FIG. 5, is equipped with a CMOS inverter IV1 including a P-channel MOS transistor MP4 and an N-channel MOS transistor MN4, and with a P-channel MOS transistor MP3 and an N-channel MOS transistor MN3 which function as the current source for the CMOS inverter IV1.
Specifically, the P-channel MOS transistor MP4 has its gate terminal connected to an input terminal (IN) of the inverter circuit U21, its drain terminal connected to an output terminal (OUT) of the inverter circuit U21, and its source terminal connected to the power supply potential via the P-channel MOS transistor MP3. The N-channel MOS transistor MN4 has its gate terminal connected to an input terminal (IN) of the inverter circuit U21, its drain terminal connected to an output terminal (OUT) of the inverter circuit U21, and its source terminal connected to the ground potential via the N-channel MOS transistor MN3.
The P-channel MOS transistor MP3 and N-channel MOS transistor MN3 that function as the current source for the CMOS inverter IV1 are configured so that their current values can be varied by a control voltage Vin. This configuration is explained below.
Namely, an N-channel MOS transistor MN1 forms a source follower and generates at both ends of a resistor R a voltage value which is approximately equal to the voltage (Vinxe2x88x92Vt) of the control voltage Vin with the threshold voltage Vt of the MOS transistor MN1 subtracted. Hence, a current I1=(Vinxe2x88x92Vt)/R which varies according to the control voltage Vin flows in the N-channel MOS transistor MN1 and the P-channel MOS transistor MP1.
The P-channel MOS transistors MP1 and MP2 constitute current mirrors. Hence, a current I2 equal to the current I1 also flows in the P-channel MOS transistor MP2 and the N-channel MOS transistor MN2. Furthermore, the P-channel MOS transistors MP1 and MP3, and the N-channel MOS transistors MN2 and MN3 also constitute current mirrors. Therefore, the P-channel MOS transistor MP3 and the N-channel MOS transistor MN3 both become a current source that outputs a current I3 equal to the current I1.
An example of operations of a conventional variable frequency type ring oscillator circuit shown in FIG. 5 is described next.
If a voltage signal at the xe2x80x9cLxe2x80x9d level is input to the input terminal (IN) of the inverter circuit U21, the P-channel MOS transistor MP4 constituting a switching unit turns ON, the N-channel transistor MN4 turns OFF, and a current I3 is output from the output terminal (OUT). Conversely, if a voltage signal at the xe2x80x9cHxe2x80x9d level is input to the input terminal (IN) of the inverter circuit U21, the P-channel MOS transistor MP4 turns OFF, the N-channel transistor MN4 turns ON, and a current I3 is drawn in through the output terminal (OUT).
The propagation delay time xcfx84 of the inverter circuit U21 is expressed by the following approximation formula:
xcfx84=C(Vdd/2)/I3(1)
where C indicates the output capacitance of the inverter circuit U21, and Vdd the power supply voltage. Hence, the oscillation frequency f of the variable frequency type ring oscillator circuit in FIG. 5 is given by the following equation:
f=1/(2Kxc2x7xcfx84)=I3/(Kxc2x7Cxc2x7Vdd)(2)
where K indicates the number of connections of the inverter circuit.
Therefore, the ring oscillator circuit has a mechanism where the oscillation frequency f can be varied by making the current I3 of the current source variable, namely by making the control voltage Vin variable.
FIG. 6 is a figure showing an example of conventional variable delay circuits. In FIG. 6, Sin indicates an input signal, and Sout a delay output signal.
As shown in FIG. 6, the delay circuit comprises K units of inverter circuits U21, U22, . . . , U2K connected in cascade.
In this instance, the delay circuit is completely the same with the variable frequency type ring oscillation circuit in a configuration other than the point that the output of the last-stage inverter circuit U2K is not fed back to the first-stage inverter circuit U21. Therefore, a detailed explanation is omitted.
In a delay circuit having such a configuration, because the propagation delay time xcfx84 of the inverter circuit U21 is given by the formula (1), its delay time t becomes as shown in the following formula:
t=Kxc2x7xcfx84=Kxc2x7C(Vdd/2)/I3xe2x80x83xe2x80x83(3) 
Therefore, the delay circuit has a mechanism where the delay time t can be varied by making the current I3 of the current source variable, namely making the control voltage Vin variable.
In conventional variable frequency type ring oscillator circuits and variable delay circuits, as stated earlier, the propagation delay time xcfx84 of each inverter circuit is an amount proportional to the power supply voltage Vdd.
As the result, in a variable frequency type ring oscillator circuit, the oscillation frequency f varies in inverse proportion to the power supply voltage Vdd. Also, in a variable delay circuit, the delay time t varies in proportion to the power supply voltage Vdd.
Therefore, there has been an inconvenience with conventional variable frequency type ring oscillator circuits and conventional variable delay circuits in that a fluctuation occurs to the oscillation frequency f or delay time t if the power supply voltage Vdd varies along with the operations of the peripheral circuit.
Hence, if a variable frequency type ring oscillator circuit is used in a PLL (phase locked loop) or if a variable delay circuit is used in a DLL (delay locked loop) for example, the phase of the signal fluctuates due to a variation of the power supply voltage Vdd, decreasing the operation reliability of any system using these circuits.
The first objective of the present invention is to provide a ring oscillator circuit that can reduce the power supply voltage dependency of the oscillation frequency.
Also, the second objective of the present invention is to provide a delay circuit that can reduce the power supply voltage dependency of the delay time.
In order to overcome these problems and to achieve the first objective of the present invention, the inventions described in claim 1-claim 4 are configured as follows.
The invention described in claim 1 is a ring oscillator circuit comprising an odd number of inverter circuits connected in a ring shape. The inverter circuit contains a first switching unit which includes at least two MOS transistors, a current source for the first switching unit, and the second switching unit which is installed in parallel to the first switching unit and includes at least two MOS transistors. The first switching unit and the second switching unit have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim 2 is a ring oscillator circuit comprising an odd number of inverter circuits connected in a ring shape. The inverter circuit contains a first CMOS inverter, a current source for the first CMOS inverter, and a second CMOS inverter which is installed in parallel to the first CMOS inverter. The first CMOS inverter and the second CMOS inverter have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim 3 is a ring oscillator circuit comprising an odd number of inverter circuits connected in a ring shape. The inverter circuit contains a first differential inverter which includes a pair of CMOS inverters, a current source for the first differential inverter, and a second differential inverter which is installed in parallel to the first differential inverter and includes a pair of CMOS inverters. The first differential inverter and the second differential inverter have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim 4 is a ring oscillator circuit described in one of the claims 1-3, where the current source is made capable of varying its current.
By having the ring oscillator circuit of the present invention have such a configuration, it becomes possible to make the rate of change in oscillation frequency against change of the power supply voltage zero near the operating point. Therefore, even if the power supply voltage varies somewhat, the oscillation frequency never varies.
In order to achieve the second objective of the present invention, the inventions described in claim 5-claim 8 are configured as follows.
The invention described in claim 5 is a delay circuit comprising a plural number of inverter circuits connected in cascade. The inverter circuit contains a first switching unit including at least two MOS transistors, a current source for the first switching unit, and a second switching unit which is installed in parallel to the first switching unit and includes at least two MOS transistors. The first switching unit and the second switching unit have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim 6 is a delay circuit comprising a plural number of inverter circuits connected in cascade. The inverter circuit contains a first CMOS inverter, a current source for the first CMOS inverter, and a second CMOS inverter which is installed in parallel to the first CMOS inverter. The first CMOS inverter and the second CMOS inverter have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim 7 is a delay circuit comprising a plural number of inverter circuits connected in cascade. The inverter circuit contains a first differential inverter including a pair of CMOS inverters, a current source for the first differential inverter, and a second differential inverter which is installed in parallel to the first differential inverter and includes a pair of CMOS inverters. The first differential inverter and the second differential inverter have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim 8 is a delay circuit described in one of the claims 5-7, where the current source is made capable of varying its current.
By having the delay circuit of the present invention have such a configuration, it becomes possible to make the rate of change in delay time against change of the power supply voltage zero near the operating point. Therefore, even if the power supply voltage varies somewhat, the delay time never varies.